Non-volatile memory systems, such as solid state drives (SSDs) including NAND flash memory, are commonly used in electronic systems ranging from consumer products to enterprise-level computer systems. Controllers in some SSDs often manage high throughput data traffic between one or more hosts and the multiple non-volatile memory die in the SSD. The high throughput combined with larger numbers of non-volatile memory die can result in processing demands in the SSD that lead to the need for a multi-processor controller.
Additionally, modern high-performance storage devices such as the SSDs mentioned above often include a volatile dynamic random access memory (DRAM) cache used to store address tables, executable firmware code, and other data. This cache is often susceptible to bit flips, and as such needs protection. One approach for handling bit flips in data is to provide end to end error protection for any type of data that is read from or written to DRAM. The end to end protection includes specialty hardware positioned in the data path that can detect and correct errors in real time. In some memory controller architectures, the specialty hardware, sometimes referred to as an error correction code (ECC) engine, may not be included in the data path used to access and store processor firmware.